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Memory architecture
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#	Item
651	The CHERI capability model: Revisiting RISC in an age of risk Jonathan Woodruff† Robert N. M. Watson† David Chisnall† Simon W. Moore† Jonathan Anderson† Brooks Davis‡ Ben Laurie§ Peter G. Neumann‡ Robert N Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2014-04-21 05:53:40 Computer memory Virtual memory Central processing unit Instruction set architectures Memory management Pointer Memory management unit MIPS architecture Memory protection Computer architecture Computing Computer hardware
652	Performance Characteristics of the POWER8™ Processor Alex Mericas Systems Performance IBM Systems & Technology Group Development Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2014-08-15 19:04:06 Cache Central processing unit Computer memory Intel Core POWER7 Microprocessors PowerPC 400 Xeon Computer hardware Computer architecture CPU cache
653	Globus GridFTP: What’s New in[removed]Invited Paper) John Bresnahan1,2,3, Michael Link1,2, Gaurav Khanna4, Zulfikar Imani3, Rajkumar Kettimuthu1,2 and Ian Foster1,2,3 1 Mathematics and Computer Science Division, Argonne Add to Reading List Source URL: toolkit.globus.org Language: English - Date: 2007-09-25 13:12:18 FTP Network performance Computer networks Supercomputers Grid computing GridFTP Globus Toolkit Transmission Control Protocol Remote direct memory access Computing Network architecture OSI protocols
654	The Stanford Hydra CMP Lance Hammond, Ben Hubbert, Michael Siu, Manohar Prabhu, Mark Willey, Michael Chen, Maciek Kozyrczak, and Kunle Olukotun Computer Systems Laboratory Stanford University http://www-hydra.stanford.e Add to Reading List Source URL: www.hotchips.org Language: English* - Date: 2013-07-27 22:49:04 CPU cache Central processing unit Multi-core processor Dynamic random-access memory Direct memory access Harvard architecture Computer hardware Computer memory Computing
655	The odd kid on the block or: to boldly run ARM like no one did before Martin Husemann [removed] Abstract Modern ARM SoCs offer bi-endian support: the CPU can switch between little and big endian mode. Similar to Add to Reading List Source URL: netbsd.org Language: English - Date: 2015-03-17 05:18:30 Instruction set architectures Computer errors Computer memory Data transmission Endianness Metaphors GNU Debugger Magic number Segmentation fault Computing Computer architecture Computer programming
656	Preventing Synergistic Processor Element Indefinite Stalls Resulting from Instruction Depletion in the Cell Broadband Engine Processor for CMOS SOI 90 nm Applications Note Add to Reading List Source URL: cell.scei.co.jp Language: English - Date: 2009-11-06 03:19:04 Computing Cell Instruction prefetch Hazard Direct memory access Computer hardware Computer architecture Computer memory
657	[New text for In-Memory for Vol. 6 Reference architecture] Platforms The platform element consists of the logical data organization and distribution combined with the associated access APIs or methods. That organization Add to Reading List Source URL: bigdatawg.nist.gov Language: English - Date: 2015-02-02 14:46:57 System software Database theory Emerging technologies Computer memory Big data Transaction processing In-memory database Database Computer data storage Database management systems Technology Data management
658	Design of a Hypermedia Interface Translating between Associative and Formal Representations Francis HEYLIGHEN* PESP, Free University of Brussels, Pleinlaan 2, B-1050 Brussels, Belgium ABSTRACT. It is argued that in orde Add to Reading List Source URL: cleamc11.vub.ac.be Language: English - Date: 2014-05-02 12:27:20 Cognitive architecture User interface Semantics Usability C dynamic memory allocation Cognition Computing Adaptive educational hypermedia Adaptive hypermedia Human–computer interaction Software ACT-R
659	The Au1000 Internet Edge Processor: TM A High Performance, Low Power SOC The First Chip in a Family of Parts from Alchemy Semiconductor, Inc. Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 23:37:56 Central processing unit Computer memory Instruction set architectures Microprocessors CPU cache Cache MIPS architecture Microarchitecture Cell Computer architecture Computer hardware Computer engineering
660	The NUMAchine Multiprocessor Z. Vranesic, S. Brown, M. Stumm, S. Caranci, A. Grbic, R. Grindley, M. Gusat, O. Krieger, G. Lemieux, K. Loveless, N. Manjikian Z. Zilic, T. Abdelrahman, B. Gamsa, P. Pereira, K. Sevcik, A. E Add to Reading List Source URL: www.eecg.toronto.edu Language: English - Date: 1999-09-21 22:20:55 Computer hardware Computer architecture Parallel computing CPU cache Cache Central processing unit Non-Uniform Memory Access Cell Memory hierarchy Computing Cache coherency Computer memory

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